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dc.contributor.advisorJacob White and Taylor Hogan.en_US
dc.contributor.authorZumbo, Zachary J.en_US
dc.contributor.otherMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.en_US
dc.date.accessioned2021-02-19T20:25:04Z
dc.date.available2021-02-19T20:25:04Z
dc.date.copyright2020en_US
dc.date.issued2020en_US
dc.identifier.urihttps://hdl.handle.net/1721.1/129860
dc.descriptionThesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, February, 2020en_US
dc.descriptionCataloged from student-submitted PDF of thesis.en_US
dc.descriptionIncludes bibliographical references (page 28).en_US
dc.description.abstractTo meet increased demand and higher PCB design expectations, research engineers have been tasked to develop models to automate PCB placement and routing procedures using machine learning and artificial intelligence techniques. Since placement and routing are still tedious manual processes which limit the design search space, these techniques allow engineers to quickly investigate better solutions. The Move37 team within Cadence Design Systems found via placement to be a crucial problem to be solved and integrated into their OrbitIO platform. We evaluated multiple non-gradient-based optimization strategies and compiled data of their performance. From these tests, a genetic algorithm-based strategy was sought due to its fast convergence and the ability to substitute cost functions. In this study, we converted the via placement problem to a simpler layer assignment problem by enforcing the location of vias and pins to be the same. We then determined an optimal layer assignment given a set of flylines, i.e. logical connections, using a genetic optimization library called DEAP. We coined this genetic optimization approach to via strategy GO VIA.en_US
dc.description.statementofresponsibilityby Zachary J. Zumbo.en_US
dc.format.extent29 pagesen_US
dc.language.isoengen_US
dc.publisherMassachusetts Institute of Technologyen_US
dc.rightsMIT theses may be protected by copyright. Please reuse MIT thesis content according to the MIT Libraries Permissions Policy, which is available through the URL provided.en_US
dc.rights.urihttp://dspace.mit.edu/handle/1721.1/7582en_US
dc.subjectElectrical Engineering and Computer Science.en_US
dc.titleGenetic optimization applied to via and route strategyen_US
dc.typeThesisen_US
dc.description.degreeM. Eng.en_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Scienceen_US
dc.identifier.oclc1237567722en_US
dc.description.collectionM.Eng. Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Scienceen_US
dspace.imported2021-02-19T20:24:34Zen_US
mit.thesis.degreeMasteren_US
mit.thesis.departmentEECSen_US


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