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dc.contributor.advisorGill A. Pratt.en_US
dc.contributor.authorHuang, Andrew S. (Andrew Shane)en_US
dc.date.accessioned2005-05-19T14:17:24Z
dc.date.available2005-05-19T14:17:24Z
dc.date.copyright1997en_US
dc.date.issued1997en_US
dc.identifier.urihttp://hdl.handle.net/1721.1/16708
dc.descriptionThesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1997.en_US
dc.descriptionIncludes bibliographical references (p. 107-109).en_US
dc.descriptionThis electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.en_US
dc.description.statementofresponsibilityby Andrew S. Huang.en_US
dc.format.extent109 p.en_US
dc.format.extent403254 bytes
dc.format.extent403011 bytes
dc.format.mimetypeapplication/pdf
dc.format.mimetypeapplication/pdf
dc.language.isoengen_US
dc.publisherMassachusetts Institute of Technologyen_US
dc.rightsM.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.en_US
dc.rights.urihttp://dspace.mit.edu/handle/1721.1/7582
dc.subjectElectrical Engineering and Computer Scienceen_US
dc.titleTao--an architecturally balanced reconfigurable hardware processoren_US
dc.typeThesisen_US
dc.description.degreeM.Eng.en_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
dc.identifier.oclc38277249en_US


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