Advanced Search
DSpace@MIT

Radio frequency digital to analog converter

Research and Teaching Output of the MIT Community

Show simple item record

dc.contributor.advisor Hae-Seung Lee. en_US
dc.contributor.author Luschas, Susan, 1975- en_US
dc.contributor.other Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. en_US
dc.date.accessioned 2005-09-26T19:31:07Z
dc.date.available 2005-09-26T19:31:07Z
dc.date.copyright 2003 en_US
dc.date.issued 2003 en_US
dc.identifier.uri http://hdl.handle.net/1721.1/28277
dc.description Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003. en_US
dc.description Includes bibliographical references (p. 124-126). en_US
dc.description.abstract Dynamic performance of high speed, high resolution digital-to-analog converters (DACs) is limited by distortion at the data switching instants. Inter-symbol interference (ISI), imperfect timing synchronization and clock jitter are all culprits. A DAC output current controlled by an oscillating waveform is proposed to mitigate the effects of the switching distortion. The oscillating waveform should be a multiple (k*fs) of the sampling frequency (f), where k>l. The waveforms can be aligned so that the data switching occurs in the zero regions of the oscillating output. This makes the DAC insensitive to switch dynamics and jitter. The architecture has the additional benefit of mixing the DAC impulse response energy to a higher frequency. An image of a low IF input signal can therefore be output directly at a high IF or RF frequency for transmit communications applications. A narrow-band sigma-delta DAC with eight unit elements is chosen to demonstrate the radio frequency digital-to-analog converter (RF DAC) concept. A sigma-delta architecture allows the current source transistors to be smaller since mismatch shaping is employed. Smaller current source transistors have a lower drain capacitance, allowing large high frequency output impedance to be achieved without an extra cascode transistor. Elimination of the cascode reduces transistor headroom requirements and allows the DAC to be built with a 1.8V supply. The RF DAC prototype is targeted to GSM transmit specifications and implemented in 0.1 8ptm CMOS technology. Measured single-tone SFDR is -75dBc, SNR is 52dB, and IMD3 is -70.8dBc over a 17.5MHz bandwidth centered at 942.5MHz. Measured SNR has the predicted dependence on the phase alignment of the data clock and oscillating pulse. en_US
dc.description.statementofresponsibility by Susan Luschas. en_US
dc.format.extent 126 p. en_US
dc.format.extent 8152848 bytes
dc.format.extent 8168717 bytes
dc.format.mimetype application/pdf
dc.format.mimetype application/pdf
dc.language.iso en_US
dc.publisher Massachusetts Institute of Technology en_US
dc.rights M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. en_US
dc.rights.uri http://dspace.mit.edu/handle/1721.1/7582
dc.subject Electrical Engineering and Computer Science. en_US
dc.title Radio frequency digital to analog converter en_US
dc.title.alternative RF DAC en_US
dc.type Thesis en_US
dc.description.degree Ph.D. en_US
dc.contributor.department Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. en_US
dc.identifier.oclc 53278026 en_US


Files in this item

Name Size Format Description
53278026.pdf 12.36Mb PDF Preview, non-printable (open to all)
53278026-MIT.pdf 12.35Mb PDF Full printable version (MIT only)

This item appears in the following Collection(s)

Show simple item record

MIT-Mirage