The bias-stress effect in pentacene organic thin-film transistors

Abstract

Organic thin-film transistors (OTFTs) are promising for flexible large-area electronics. However, the bias-stress effect (BSE) in OTFTs causes operational instability that limits the usefulness of the OTFT technology in a wide range of circuit applications. Currently, most existing studies on OTFT BSE are inadequate because of one or more of the following reasons. First, they study the BSE on OTFTs with thermally grown Si0 2, which cannot be used in flexible electronics due to its high deposition temperature. Secondly, they use devices with no encapsulation, and the devices degrade by exposure to H₂0 and 0₂ in ambient air. The existence of such other degradation mechanisms complicates the interpretation of the BSE measurements on these devices. Lastly, they do not study the BSE systematically to fully identify its dependencies on various stress conditions. This work addresses these issues by systematically studying the electrical characteristics of the BSE in integrated pentacene OTFTs with polymer gate dielectric and encapsulation. Pentacene is used as the model organic semiconductor because it is the most widely used organic semiconductor for OTFTs. The measurements reveal that the BSE results from carriers that are trapped at the semiconductor/dielectric interface. The BSE can be accurately modeled by a shift in the gate voltage, [delta]V, which equals qN/Ci, where N is the density of trapped carriers, and Ci is the channel capacitance per unit area. The BSE occurs only when both gate field and channel carriers are present and the drain current does not increase the BSE. Because the density of traps is limited, when there are more carriers induced in the channel than available number of traps, AV saturates at a constant value, which is directly proportional to the trap density in the channel.

(cont.) This behavior of [delta]V saturation despite the presence of free carriers in the channel is observed for the first time in a TFT. Through the temperature measurements, we identify that the source of the long time constants for trapping is the high energy barriers for carriers to be trapped. The effective energy barrier is found to be 0.8 eV for the measured pentacene OTFTs. The time constants associated with the traps are dispersed due to the disorder in the pentacene and gate dielectric. The dependencies of the BSE to various stress conditions are modeled, which allows prediction of [delta]V for different stress times and voltages. The model is used to estimate the implication of the BSE on circuit applications and usable lifetime. Full recovery of the original I-V characteristics occur when the bias stress is removed. The recovery is found to have time dependency and thermal activation energy that is similar to the BSE implying that the recovery mechanism is similar to that of the BSE. The application of the negative VSG accelerates recovery, which serves as evidence that the recovery is achieved by detrapping of the trapped carrier. Possible mechanisms for the BSE and its recovery are discussed based on the experimental observations. A new annealing process which improves mobility, contact resistance, and operational stability has been developed. Experimentally the annealing process increased mobility from 0.03 to 0.05 cm2/Vs and decreased contact resistance from 185 to 38 K[ohm]-cm. The overall improvement in stability is over eight times for a wide range of stress conditions. The stability is found to be increased by the reduction of the trap density and the decrease of the trapping rate.