MIT Libraries logoDSpace@MIT

MIT
View Item 
  • DSpace@MIT Home
  • MIT Libraries
  • MIT Theses
  • Graduate Theses
  • View Item
  • DSpace@MIT Home
  • MIT Libraries
  • MIT Theses
  • Graduate Theses
  • View Item
JavaScript is disabled for your browser. Some features of this site may not work without it.

45nm direct battery DC-DC converter for mobile applications

Author(s)
Bandyopadhyay, Saurav
Thumbnail
DownloadFull printable version (6.689Mb)
Alternative title
Forty five nm direct battery Direct Current-Direct Current converter for mobile applications
Other Contributors
Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
Advisor
Anantha P. Chandrakasan.
Terms of use
M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582
Metadata
Show full item record
Abstract
Portable devices use Lithium-ion batteries as the energy source due to their high energy density, long cycle life and low memory effects. With the aggressive downscaling of CMOS, it is becoming increasingly difficult to efficiently interface the low voltage, low power digital baseband and DSP of the mobile phone with the battery which maybe at voltages as high as 4.2V. This is efficiently done by a DC-DC converter which is a separate IC designed on an older generation process capable of handling high voltages. However, this requires an extra IC, thereby increasing the overall system cost. Here, a buck converter is demonstrated on a standard 45nm digital CMOS process which can be integrated with the 45nm digital core on the same die. This converter is capable of handling high battery voltages (2.8V to 4.2V) and delivers a regulated low voltage (0.5V to 1.1V) to the digital core. The converter can supply 20[mu]A to 100mA of load current. The peak efficiency of the converter is 87% for 73mW output at 4.2V supply and for the ultra low power levels, efficiency of 75% is obtained for a 20[mu]W load at 3V. Both pulse width modulation (PWM) and pulse frequency modulation (PFM) modes of control are used. A new digital pulse width modulator (DPWM) architecture is presented which provides 75% area savings over the conventional delay line and counter based architecture with comparable power consumption. The buck converter also requires Switched Capacitor (SC) DC-DC Converters to generate stacking regulators and regulator for the control circuitry. On the whole, the complete system integrates the Power Management Unit with the core for a single chip radio in 45nm.
Description
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2010.
 
Includes bibliographical references (p. 65-66).
 
Date issued
2010
URI
http://hdl.handle.net/1721.1/60149
Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Publisher
Massachusetts Institute of Technology
Keywords
Electrical Engineering and Computer Science.

Collections
  • Graduate Theses

Browse

All of DSpaceCommunities & CollectionsBy Issue DateAuthorsTitlesSubjectsThis CollectionBy Issue DateAuthorsTitlesSubjects

My Account

Login

Statistics

OA StatisticsStatistics by CountryStatistics by Department
MIT Libraries
PrivacyPermissionsAccessibilityContact us
MIT
Content created by the MIT Libraries, CC BY-NC unless otherwise noted. Notify us about copyright concerns.