Concurrent gate-level circuit simulation
Author(s)
Shelly, Jacinda R. (Jacinda Rene)
DownloadFull printable version (3.144Mb)
Alternative title
Concurrent Gsim
Other Contributors
Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
Advisor
Christopher J. Terman.
Terms of use
Metadata
Show full item recordAbstract
In the last several years, parallel computing on multicore processors has transformed from a niche discipline relegated primarily to scientific computing into a standard component of highperformance personal computers. At the same time, simulating processors prior to manufacture has become increasingly time-consuming due to the increasing number of gates on a single chip. However, writing parallel programs in a way that significantly improves performance can be a difficult task. In this thesis, I outline principles that must be considered when running good gate-level circuit simulations in parallel. I also analyze a test circuit's performance in order to quantitatively demonstrate the benefit of considering these principles in advance of running simulations.
Description
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2010. Cataloged from PDF version of thesis. Includes bibliographical references (p. 42).
Date issued
2010Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer SciencePublisher
Massachusetts Institute of Technology
Keywords
Electrical Engineering and Computer Science.