Designing and implementing a readout strategy for superconducting single photon detectors

Abstract

Introduction: Photon detection is an integral part of experimental physics, high-speed communication, as well as many other high-tech disciplines. In the realm of communication, unmanned spacecraft are travelling extreme distances, and ground stations need more and more sensitive and selective detectors to maintain a reasonable data rate.[10] In the realm of computing, some of the most promising new forms of quantum computing require consistent and efficient optical detection of single entangled photons.[27] Due to projects like these, demands are increasing for ever more efficient detectors with higher count rates. The Superconducting Nanowire Single-Photon Detector (SNSPD) is one of the most promising new technologies in this field, being capable of counting photons as faster than 100MHz and with efficiencies around 50%. Currently, the leading competition is from the geiger-mode avalanche photodiode, which is capable of ~20- 70% efficiency at a ~5MHz count rate depending on photon energy. In spite of these advantages, the SNSPD is still a brand-new technology and as a result they do not have the same support hardware support as other detectors. As such, SNSPD's are much more difficult to integrate into an existing an experiment. Because of this difficulty, SNSPD's have not been deployed extensively for research or industrial applications. The signal analysis chain that is connected to this detector is one of the key choke points. Each detector count produces a 0.1 mV, 10 nS wide pulse with a maximum count frequency on the order of 100MHz. Currently, this signal is processed outside of the cryostat with a series of RF amplifiers and a high-speed counter. This design works for detector prototyping, but poses a series of problems with actual design implementation. Most importantly, it prevents our design from being scalable. Even though we can fabricate thousands of detectors on a single wafer, it would be extremely difficult to place that many RF lines without crosstalk or other interference. The purpose of this thesis is to build a more robust and scalable readout technology for SNSPDs. First, we will develop intermediate technologies that improve upon current readout technology and will be necessary to develop the final goal. Ultimately, we plan to build circuitry on-chip that will first convert each detector's analog signal to a digital signal and then condense the data from each detector into an externally clocked, single-bit output indicating the presence or absence of a photon at any detector. This will allow simultaneous readout of a large number of detectors on a single wafer. Additionally, our cryogenic will decrease the noise observed by the detector, as the amplifier is no longer operating at room temperature. Finally, our readout will provide a simple hardware API to be interfaced to a computer or embedded processing unit. The catch to this development process is that the entire system must operate at 4.2K or below. As such, one must either use HEMT CMOS or Rapid Single-Flux- Quantum (RSFQ) logic. HEMT CMOS is better suited to analog amplification of the output signal, while RSFQ circuitry is better suited to the construction of the SNSPD interface and digital logic. RSFQ circuitry is better suited as an input stage because input amplification with CMOS is difficult, as one must operate in the linear regime of a HEMT. This requires on the order of 1 mA at 1.8 V minimum, which results in approximately 2 mW per stage. This is to be compared against RSFQ comparators which utilize approximately 0.5 mA at almost no voltage, resulting in muW of dissipation per stage. Given that we are hoping to produce a large number of SNSPD input stages, RSFQ is clearly a better choice. However, we only have a small number of output signals from the cryostat, so it is much more reasonable to use CMOS, as we can attain larger signal amplitudes.