Design of ultra low power analog-to-digital converter for ambulatory EEG recording

Abstract

Portable acquisition of biopotential signals requires the design of compact, energy efficient circuits and systems. Such systems typically include analog-to-digital converter for digitizing signals from AFE and feeding it to DBE. An Ultra low power ADC is designed in this work to be integrated within scalable EEG SoC. The full system can capture EEG signals through 1 up to 8 parallel differential channels that are time division multiplexed into a single ADC. The ADC has a fixed resolution of 10 bits which is sufficient for extraction of bio-markers for seizure detection. A SAR ADC architecture is chosen for this design as it is highly energy efficient for medium to high resolution applications with low speed requirements. A differential capacitive DAC is utilized to enhance the CMRR. Concepts of split-capacitor array and sub-DAC are combined to reduce the DAC area and power consumption. Charge pumps are used to boost the control voltage of sampling switches. The ADC performs a conversion every 16 clock cycle while being governed by a self-resetting SAR logic. The sampling rate can be scaled up to 32 kHz by varying the clock frequency to accommodate different number of channels used. The ADC was designed and fabricated in a 0.18 pm CMOS technology. The entire ADC core consumes 1 pW from 1 V supply at a sampling rate of 32 kHz. The ADC has a maximum DNL and INL of 0.55 LSB and 0.75 LSB respectively. The SNDR and SFDR of the converter are measured at a sampling rate of 32 kHz and 15.5 kHz input tone to be 57.9 dB and 68.5 dBFS respectively. The ADC FOM is 51 fJ/Conv-Step.