Fundamental limits of the switching abruptness of tunneling transistors

Abstract

The tunneling field-effect transistor (TFET) is one of the most promising candidates for future low-power electronics because of its potential to achieve a subthreshold swing less than the 60 mV/decade thermal limit at room temperature. It can surpass this limit because the turn-on of tunneling does not sample the Maxwell-Boltzmann distribution of carriers that gives rise to the 60 mV/decade limit in conventional devices. However, theoretical predictions and experimental measurements of TFET device characteristics have differed by a wide margin-experimental subthreshold characteristics have not achieved the switching steepness (i.e., the change in drain current with applied gate voltage) of theoretical simulations. Non-ideal effects, such as non-abrupt band edges, phonon-assisted tunneling, and trap states, are discussed as mechanisms that may degrade theoretical predications. A strained-Si/strained-Ge bilayer TFET is used as a test-bed device to better understand the discrepancy between simulation and experiment. The bilayer TFET studied in this work eliminates channel doping and uses the strained-Si/strained-Ge heterostructure. Band-to-band tunneling occurs perpendicular to the gate, in-line with the gate electric field. Multiple gates are used so that the impact of the directionality of tunneling on switching abruptness can be studied. The band alignment of the strained-Si/strained-Ge heterostructure is extracted from a MOS-capacitor structure though an experimental quasistatic CV technique. The extracted effective band gap (related to the tunneling barrier) is shown to be only -200 meV for the heterostructure, and the valence band offset is shown to be -100 meV larger than predicted by density-functional theory. New deformation potentials are suggested for the Si-Ge material system based on the experimentally extracted band alignments. The impact of quantization on the turn-on voltage and gate-leakage current in a thin-body bilayer TFET structure is studied, and large confinement energy is shown to be especially problematic at body thicknesses less than 10 nm. An InAs structure with a body thickness less than 7 nm is shown to require a larger turn-on voltage than either Si or Ge homostructures due to the very light electron mass in InAs that leads to a large confinement energy. The strained- Si/strained-Ge heterostructure is shown to dramatically reduce the turn-on voltage due to its small effective band gap. Quantization is shown to limit the gate efficiency since increasing the body voltage, in order to align the electron and hole eigenstates in energy, increases the electric field across the structure, which in turn increases quantization. Gate leakage current increases exponentially as the body thickness decreases because the body voltage (and hence, the electric field) at turn-on increases with decreasing body thickness and gate leakage is exponentially dependent on the electric field. Non-ideal two-dimensional effects are investigated as mechanisms that degrade the switching characteristics of perpendicular TFETs (i.e. devices with tunneling perpendicular to the gate). Abrupt termination of a heavily doped semiconductor layer, often present in perpendicular TFET structures, can lead to large in-plane electric fields that give rise to parasitic diagonal tunneling paths, as opposed to the desired perpendicular tunneling paths. While the turn-on of each leakage path may be individually sharp, the sum of all tunneling paths is smeared by the multiple turn-ons and results in a degraded transfer characteristic for the device. The characteristic length, used for determining the length scale of potential fluctuations in short-channel MOSFETs, is suggested as a parameter that can be used to evaluate the likelihood of parasitic tunneling paths in a perpendicular TFET structure. The fabrication of the 3Gate strained-Si/strained-Ge bilayer TFET is detailed. The process includes epitaxial growth of a highly strained heterostructure, planarization of a bottom gate, wafer bonding of an epitaxial wafer to a handle wafer, etch-back of the epitaxial wafer leaving the thin strained-Si/strained-Ge heterostructure, and standard processing to create devices. Future work on electrical characterization of the experimental 3Gate bilayer TFET is discussed. Several test configurations are suggested as a way to probe the effects of diagonal tunneling on the abruptness of the switching characteristics.