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Design Considerations for Efficient Deep Neural Networks on Processing-in-Memory Accelerators

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sword-2021-04-15T16:58:16.original.xml (130 B)
Original SWORD entry document
Date Issued
December 2020
Journal
Technical Digest - International Electron Devices Meeting, IEDM
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
2020. "Design Considerations for Efficient Deep Neural Networks on Processing-in-Memory Accelerators." Technical Digest - International Electron Devices Meeting, IEDM, 2019-December.
Version
Author's final manuscript
Abstract
© 2019 IEEE. This paper describes various design considerations for deep neural networks that enable them to operate efficiently and accurately on processing-in-memory accelerators. We highlight important properties of these accelerators and the resulting design considerations using experiments conducted on various state-of-the- art deep neural networks with the large-scale ImageNet dataset.
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Creative Commons Attribution-Noncommercial-Share Alike
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DOI of Published Version
10.1109/IEDM19573.2019.8993662
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