Full utilization, fairness, and access delay on high speed slotted bus networks

Author(s)
Chiu, Angela Lan
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Massachusetts Institute of Technology. Laboratory for Information and Decision Systems.
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Description
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1997.
 
Includes bibliographical references (p. 89-92).
 
Date issued
1997
URI
http://hdl.handle.net/1721.1/10699
Department
Massachusetts Institute of Technology. Laboratory for Information and Decision Systems; Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Publisher
Massachusetts Institute of Technology, Laboratory for Information and Decision SystemsMassachusetts Institute of Technology
Other identifiers
2382
Series/Report no.
LIDS-P ; 2382.
Keywords
Laboratory for Information and Decision Systems.
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