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dc.contributor.authorChiu, Angela Lanen_US
dc.contributor.otherMassachusetts Institute of Technology. Laboratory for Information and Decision Systems.en_US
dc.date.accessioned2005-08-18T17:54:12Z
dc.date.available2005-08-18T17:54:12Z
dc.date.issued1997en_US
dc.identifier.other2382en_US
dc.identifier.urihttp://hdl.handle.net/1721.1/10699
dc.descriptionThesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1997.en_US
dc.descriptionIncludes bibliographical references (p. 89-92).en_US
dc.description.sponsorshipSupported by the U.S. Army Research Office. ARO ASSERT DAAH04-94-G-0221 Supported by National Science Foundation. NCR-92036379 Supported by Advanced Research Project Agency. MDA972-92-J-1038en_US
dc.description.statementofresponsibilityChiu, A.L.en_US
dc.format.extent92 p.en_US
dc.format.extent4619469 bytes
dc.format.extent4619227 bytes
dc.format.mimetypeapplication/pdf
dc.format.mimetypeapplication/pdf
dc.language.isoengen_US
dc.publisherMassachusetts Institute of Technology, Laboratory for Information and Decision Systemsen_US
dc.publisherMassachusetts Institute of Technologyen_US
dc.relation.ispartofseriesLIDS-P ; 2382.en_US
dc.rightsM.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.en_US
dc.rights.urihttp://dspace.mit.edu/handle/1721.1/7582
dc.subjectLaboratory for Information and Decision Systems.en_US
dc.subject.lccTK7855.M41 E3845 no.2382en_US
dc.titleFull utilization, fairness, and access delay on high speed slotted bus networksen_US
dc.typeThesisen_US
dc.description.degreePh.D.en_US
dc.contributor.departmentMassachusetts Institute of Technology. Laboratory for Information and Decision Systemsen_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
dc.identifier.oclc36598377en_US


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