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dc.contributor.advisorAnantha P. Chandrakasan.en_US
dc.contributor.authorYaul, Frank Men_US
dc.contributor.otherMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.en_US
dc.date.accessioned2017-03-10T15:07:03Z
dc.date.available2017-03-10T15:07:03Z
dc.date.copyright2016en_US
dc.date.issued2016en_US
dc.identifier.urihttp://hdl.handle.net/1721.1/107360
dc.descriptionThesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2016.en_US
dc.descriptionCataloged from PDF version of thesis.en_US
dc.descriptionIncludes bibliographical references (pages 151-157).en_US
dc.description.abstractSensor interfaces circuits are integral components of wireless sensor nodes, and improvements to their energy-efficiency help enable long-term medical and industrial monitoring applications. This thesis explores both analog and algorithmic energy-saving techniques in the sensor interface signal chain. First, a data-dependent successive-approximation algorithm is developed and is demonstrated in a low-power analog-to-digital converter (ADC) implementation. When averaged over many samples, the energy per conversion and number of bitcycles per conversion used by this algorithm both scale logarithmically with the activity of the input signal, with each N-bit conversion using between 2 and 2N+1 bitcycles, compared to N for conventional binary SA. This algorithm reduces ADC power consumption when sampling signals with low mean activity, and its effectiveness is demonstrated on an electrocardiogram signal. With a 0.6V supply, the 10-bit ADC test chip has a maximum sample rate of 16 kHz and an effective number of bits (ENOB) of 9.73b. The ADC's Walden Figure of Merit (FoM) ranges from 3.5 to 20 fJ/conversion-step depending on the input signal activity. Second, an ultra-low supply voltage amplifier stage is developed and used to create an energy-efficient low-noise instrumentation amplifier (LNIA). This chopper LNIA uses a 0.2V-supply inverter-based input stage followed by a 0.8V-supply folded-cascode common-source stage. The high input-stage current needed to reduce the input-referred noise is drawn from the 0.2V supply, significantly reducing power consumption. The 0.8V stage provides high gain and signal swing, improving linearity. Biasing and common-mode rejection techniques for the 0.2V-stage are also presented. The analog front-end (AFE) test chip incorporating the chopper LNIA achieves a power-efficiency figure (PEF) of 1.6 with an input noise of 0.94 [mu]VRMS, integrated from 0.5 to 670 Hz. Human biopotential signals are measured using the AFE.en_US
dc.description.statementofresponsibilityby Frank M. Yaul.en_US
dc.format.extent157 pagesen_US
dc.language.isoengen_US
dc.publisherMassachusetts Institute of Technologyen_US
dc.rightsMIT theses are protected by copyright. They may be viewed, downloaded, or printed from this source but further reproduction or distribution in any format is prohibited without written permission.en_US
dc.rights.urihttp://dspace.mit.edu/handle/1721.1/7582en_US
dc.subjectElectrical Engineering and Computer Science.en_US
dc.titleAmplifier and data converter techniques for low power sensor interfacesen_US
dc.typeThesisen_US
dc.description.degreePh. D.en_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
dc.identifier.oclc973334133en_US


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