Photonics for technology : circuits, chip-scale LIDAR, and optical neural networks
Author(s)Skirlo, Scott Alexander
Circuits, chip-scale LIDAR, and optical neural networks
Massachusetts Institute of Technology. Department of Physics.
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This thesis focuses on a wide range of contemporary topics in modern electromagnetics and technology including topologically protected one-way modes, integrated photonic LIDAR, and optical neural networks. First, we numerically investigate large Chern numbers in photonic crystals and explore their origin from simultaneously gapping multiple band degeneracies. Following this, we perform microwave transmission measurements in the bulk and at the edge of ferrimagnetic photonic crystals. Bandgaps with large Chern numbers of 2, 3, and 4 are present in the experimental results 'which show excellent agreement with theory. We measure the mode profiles and Fourier transform them to produce dispersion relations of the edge modes, whose number and direction match our Chern number calculations. We use these waveguides to realize reflectionless power splitters and outline their application to general one-way circuits. Next we create a new chip-scale LIDAR architecture in analogy to planar RF lenses. Instead of relying upon many continuously tuned thermal phase shifters to implement nonmechanical beam steering, we use aplanatic lenses excited in their focal plane feeding ID gratings to generate discrete beams. We design devices which support up to 128 resolvable points in-plane and 80 resolvable points out-of-plane, which are currently being fabricated and tested. These devices have many advantages over conventional optical phased arrays including greatly increased optical output power and decreased electrical power for in-plane beamforming. Finally we explore a new approach for implementing convolutional neural networks through an integrated photonics circuit consisting of Mach-Zehnder Interferometers, optical delay lines, and optical nonlinearity units. This new platform, should be able to perform the order of a thousand inferences per second, at [mu]J power levels per inference, with the nearest state of the art ASIC and GPU competitors operating 30 times slower and requiring three orders of magnitude more power.
Thesis: Ph. D., Massachusetts Institute of Technology, Department of Physics, 2017.Cataloged from PDF version of thesis.Includes bibliographical references (pages 163-175).
DepartmentMassachusetts Institute of Technology. Department of Physics.
Massachusetts Institute of Technology