MIT Libraries logoDSpace@MIT

MIT
View Item 
  • DSpace@MIT Home
  • MIT Libraries
  • MIT Theses
  • Graduate Theses
  • View Item
  • DSpace@MIT Home
  • MIT Libraries
  • MIT Theses
  • Graduate Theses
  • View Item
JavaScript is disabled for your browser. Some features of this site may not work without it.

Terahertz beam-steering imager using a scalable 2D-coupled architecture and multi- functional heterodyne pixels

Author(s)
Zhang, Guo (Electrical and computer science engineer) Massachusetts Institute of Technology
Thumbnail
DownloadFull printable version (5.211Mb)
Other Contributors
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.
Advisor
Ruonan Han.
Terms of use
MIT theses are protected by copyright. They may be viewed, downloaded, or printed from this source but further reproduction or distribution in any format is prohibited without written permission. http://dspace.mit.edu/handle/1721.1/7582
Metadata
Show full item record
Abstract
The topic covered by this thesis is the project of designing a terahertz imager chip on nowadays commercialized mature silicon platform. In the project, we developed the design method of a multi-functional heterodyne pixel and a scalable array architecture. The pixel is a compact electromagnetic structure simultaneously performs voltage-controlled 140 GHz local oscillation, 280-GHz-signal receiving, sub-harmonic mixing, and intermediate frequency (IF) signal extraction. Each pixel consumes 10 mW power and achieves a sensitivity of 2.9 pW in simulation. The local oscillator (LO) of the pixel is phase coupled with its neighbors; the whole oscillator array is then stabilized by an on-chip THz phase-locked loop. This architecture gives excellent array scalability. First, the LO power is evenly distributed and does not degrade in a larger array scale as a normal centralized array does. Second, the phase noise of the coupled LO network improves linearly with the array size. The simulated phase noise at 1-MHz frequency offset is -90 dBc/Hz for an 8 x 8 array and -101 dBc/Hz for a 32 x 32 array. This chip is capable of digital beam steering, too. The first version of the chip prototype with a 10 x 10 array is fabricated using a 130-nm SiGe BiCMOS process and tested.
Description
Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2017.
 
Cataloged from PDF version of thesis.
 
Includes bibliographical references (pages 47-49).
 
Date issued
2017
URI
http://hdl.handle.net/1721.1/113963
Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Publisher
Massachusetts Institute of Technology
Keywords
Electrical Engineering and Computer Science.

Collections
  • Graduate Theses

Browse

All of DSpaceCommunities & CollectionsBy Issue DateAuthorsTitlesSubjectsThis CollectionBy Issue DateAuthorsTitlesSubjects

My Account

Login

Statistics

OA StatisticsStatistics by CountryStatistics by Department
MIT Libraries
PrivacyPermissionsAccessibilityContact us
MIT
Content created by the MIT Libraries, CC BY-NC unless otherwise noted. Notify us about copyright concerns.