| dc.contributor.advisor | Anant Agarwal. | en_US |
| dc.contributor.author | Bauer, Trevor Joseph | en_US |
| dc.date.accessioned | 2005-08-16T21:40:49Z | |
| dc.date.available | 2005-08-16T21:40:49Z | |
| dc.date.copyright | 1994 | en_US |
| dc.date.issued | 1994 | en_US |
| dc.identifier.uri | http://hdl.handle.net/1721.1/11983 | |
| dc.description | Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994. | en_US |
| dc.description | Includes bibliographical references (leaves 54-55). | en_US |
| dc.description.statementofresponsibility | by Trevor Joseph Bauer. | en_US |
| dc.format.extent | 55 leaves | en_US |
| dc.format.extent | 2974105 bytes | |
| dc.format.extent | 2973862 bytes | |
| dc.format.mimetype | application/pdf | |
| dc.format.mimetype | application/pdf | |
| dc.language.iso | eng | en_US |
| dc.publisher | Massachusetts Institute of Technology | en_US |
| dc.rights | M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. | en_US |
| dc.rights.uri | http://dspace.mit.edu/handle/1721.1/7582 | |
| dc.subject | Electrical Engineering and Computer Science | en_US |
| dc.title | The design of an efficient hardware subroutine protocol for FPGAs | en_US |
| dc.type | Thesis | en_US |
| dc.description.degree | M.Eng. | en_US |
| dc.contributor.department | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science | |
| dc.identifier.oclc | 31161980 | en_US |
