MIT Libraries homeMIT Libraries logoDSpace@MIT

MIT
View Item 
  • DSpace@MIT Home
  • MIT Libraries
  • MIT Theses
  • Theses - Dept. of Electrical Engineering and Computer Sciences
  • Electrical Engineering and Computer Sciences - Master's degree
  • View Item
  • DSpace@MIT Home
  • MIT Libraries
  • MIT Theses
  • Theses - Dept. of Electrical Engineering and Computer Sciences
  • Electrical Engineering and Computer Sciences - Master's degree
  • View Item
JavaScript is disabled for your browser. Some features of this site may not work without it.

Design and analysis of a 200 volt, high slew rate, current-limited operational amplifier

Author(s)
Estay Forno, Ignacio.
Thumbnail
Download1127640115-MIT.pdf (2.689Mb)
Other Contributors
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.
Advisor
Alec J. Poitzsch and Ruonan Han.
Terms of use
MIT theses are protected by copyright. They may be viewed, downloaded, or printed from this source but further reproduction or distribution in any format is prohibited without written permission. http://dspace.mit.edu/handle/1721.1/7582
Metadata
Show full item record
Abstract
This thesis is focused around the development of an amplifier with novel features in a 200 V silicon process internal to Analog Devices. Despite being on a closed-process, the discussion focuses on topological and architectural developments that are applicable to a wide range of high voltage processes. The use case examined is one whereby large capacitive loads need to be driven by high voltage analog steps anywhere in a 200 V range, with ideal slew rates measuring in the kV/s range, while having clean, adjustable current limiting and low quiescent current consumption. Several common amplifier topologies are examined, with their merits and drawbacks discussed in the context of the use case. Ultimately, a hybridized approach is taken for an input stage for the amplifier that accomplishes high slew rates at the output while maintaining accurate, adjustable current limiting. The amplifier discussed, designed, and simulated operates at a 200 V rail-to-rail potential, with up to 1 A of continuous output current, with a slew rate exceeding 1 kV/s, drawing only 25 mA quiescent, and user-adjustable current limiting that operates without the need for an inefficient in-line current-sense resistor. The current limiting blocks discussed operate with a no excess DC current or power to operate apart from a small amount supplied for current-limiting adjustability.
Description
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
 
Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2019
 
Cataloged from student-submitted PDF version of thesis.
 
Includes bibliographical references (page 95).
 
Date issued
2019
URI
https://hdl.handle.net/1721.1/123020
Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Publisher
Massachusetts Institute of Technology
Keywords
Electrical Engineering and Computer Science.

Collections
  • Electrical Engineering and Computer Sciences - Master's degree
  • Electrical Engineering and Computer Sciences - Master's degree

Browse

All of DSpaceCommunities & CollectionsBy Issue DateAuthorsTitlesSubjectsThis CollectionBy Issue DateAuthorsTitlesSubjects

My Account

Login

Statistics

OA StatisticsStatistics by CountryStatistics by Department
MIT Libraries homeMIT Libraries logo

Find us on

Twitter Facebook Instagram YouTube RSS

MIT Libraries navigation

SearchHours & locationsBorrow & requestResearch supportAbout us
PrivacyPermissionsAccessibility
MIT
Massachusetts Institute of Technology
Content created by the MIT Libraries, CC BY-NC unless otherwise noted. Notify us about copyright concerns.