Design and analysis of a 200 volt, high slew rate, current-limited operational amplifier

Abstract

This thesis is focused around the development of an amplifier with novel features in a 200 V silicon process internal to Analog Devices. Despite being on a closed-process, the discussion focuses on topological and architectural developments that are applicable to a wide range of high voltage processes. The use case examined is one whereby large capacitive loads need to be driven by high voltage analog steps anywhere in a 200 V range, with ideal slew rates measuring in the kV/s range, while having clean, adjustable current limiting and low quiescent current consumption. Several common amplifier topologies are examined, with their merits and drawbacks discussed in the context of the use case. Ultimately, a hybridized approach is taken for an input stage for the amplifier that accomplishes high slew rates at the output while maintaining accurate, adjustable current limiting. The amplifier discussed, designed, and simulated operates at a 200 V rail-to-rail potential, with up to 1 A of continuous output current, with a slew rate exceeding 1 kV/s, drawing only 25 mA quiescent, and user-adjustable current limiting that operates without the need for an inefficient in-line current-sense resistor. The current limiting blocks discussed operate with a no excess DC current or power to operate apart from a small amount supplied for current-limiting adjustability.