High-throughput computation of Shannon mutual information on chip
Author(s)Li, Peter Zhi Xuan.
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.
Vivienne Sze and Sertac Karaman.
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Exploration problems are fundamental to robotics, arising in various domains, ranging from search and rescue to space exploration. In these domains and beyond, exploration algorithms that allow the robot to rapidly create the map of the unknown environment can reduce the time and energy for the robot to complete its mission. Many eective exploration algorithms rely on the computation of Shannon mutual information (MI) which allow the robot to select the best location to explore in order to gain the most information about the unknown environment. Unfortunately, computing MI metrics is computationally challenging. In fact, a large fraction of the current literature focuses on approximation techniques to devise computationally-efficient algorithms. While the computation of MI can be parallelized and thus computed by many parallel cores, the main challenge that limits throughput is the delivery of data to these cores.As such, in this work we propose a MI hardware accelerator that has a novel memory banking pattern and an arbiter that ensure eective utilization of all MI cores to maximize throughput. In addition, our rigorous analysis of the banking pattern and arbiter ensures that our designs are near-optimal without resorting to a time-consuming, intuition-based search across a large set of hardware design parameters for verification. Finally, the proposed architecture is validated on an FPGA and implemented on an ASIC in a commercial 65nm technology. Our ASIC implementation computes the MI for an entire map from a real-world experiment of 10.05m x 10.05m at 0.05m resolution in real time at 11Hz, which is 88x and 13x faster than the ARM Cortex-A57 CPU and NVIDIA Pascal GPU on the Jetson TX2 board respectively. Furthermore, the ASIC implementation consumes 162mW, which is 21x lower and 20x lower than the ARM Cortex-A57 CPU and NVIDIA Pascal GPU on the Jetson TX2 board respectively.Using the entire MI map that is quickly computed by the ASIC, the robot is able to choose the optimal exploration trajectory during path planning such that the amount of exploration time can be reduced during time-critical missions, such as search and rescue.
Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, May, 2020Cataloged from the official PDF of thesis.Includes bibliographical references (pages 155-158).
DepartmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Massachusetts Institute of Technology
Electrical Engineering and Computer Science.