Graph preprocessing for in-memory vertex-centric graph computation on the Intel Optane DC persistent memory module
Author(s)Sun, Mengyuan,M. Eng.Massachusetts Institute of Technology.
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.
Julian Shun and Sam Madden.
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Processing graphs is the foundation for many social network analysis, optimization, and propagation problems. New hardware technologies like the Intel Optane persistent memory module allow in-memory graph processing for graphs of a larger scale compared to standard machines. This is made possible by augmenting dynamic random access memory (DRAM) with nonvolatile random access memory (NVRAM). However, even with faster-than-disk access and greater storage capabilities of NVRAM, DRAM and other faster level I/O such as cache still remain the more valuable resources. In this project, we analyze the effects of various graph partitioning and graph reordering techniques in order to find efficient data placement strategies for graphs stored between DRAM and NVRAM. The performance of graph data placement techniques varies depending on algorithm type and graph structure. We find that partitioned graphs for algorithms such as BFS can perform between 1.5-3x faster than ones with a naive data placement technique. The graph partitioning techniques that perform the best are lightweight degree ordering ones. We find that the best graph reordering techniques are heavily dependent on graph and algorithm type.
Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, September, 2020Cataloged from student-submitted PDF of thesis.Includes bibliographical references (pages 41-43).
DepartmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Massachusetts Institute of Technology
Electrical Engineering and Computer Science.