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dc.contributor.advisorJulian Shun and Sam Madden.en_US
dc.contributor.authorSun, Mengyuan,M. Eng.Massachusetts Institute of Technology.en_US
dc.contributor.otherMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.en_US
dc.date.accessioned2021-01-06T19:33:51Z
dc.date.available2021-01-06T19:33:51Z
dc.date.copyright2020en_US
dc.date.issued2020en_US
dc.identifier.urihttps://hdl.handle.net/1721.1/129228
dc.descriptionThesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, September, 2020en_US
dc.descriptionCataloged from student-submitted PDF of thesis.en_US
dc.descriptionIncludes bibliographical references (pages 41-43).en_US
dc.description.abstractProcessing graphs is the foundation for many social network analysis, optimization, and propagation problems. New hardware technologies like the Intel Optane persistent memory module allow in-memory graph processing for graphs of a larger scale compared to standard machines. This is made possible by augmenting dynamic random access memory (DRAM) with nonvolatile random access memory (NVRAM). However, even with faster-than-disk access and greater storage capabilities of NVRAM, DRAM and other faster level I/O such as cache still remain the more valuable resources. In this project, we analyze the effects of various graph partitioning and graph reordering techniques in order to find efficient data placement strategies for graphs stored between DRAM and NVRAM. The performance of graph data placement techniques varies depending on algorithm type and graph structure. We find that partitioned graphs for algorithms such as BFS can perform between 1.5-3x faster than ones with a naive data placement technique. The graph partitioning techniques that perform the best are lightweight degree ordering ones. We find that the best graph reordering techniques are heavily dependent on graph and algorithm type.en_US
dc.description.statementofresponsibilityby Mengyuan Sun.en_US
dc.format.extent55 pagesen_US
dc.language.isoengen_US
dc.publisherMassachusetts Institute of Technologyen_US
dc.rightsMIT theses may be protected by copyright. Please reuse MIT thesis content according to the MIT Libraries Permissions Policy, which is available through the URL provided.en_US
dc.rights.urihttp://dspace.mit.edu/handle/1721.1/7582en_US
dc.subjectElectrical Engineering and Computer Science.en_US
dc.titleGraph preprocessing for in-memory vertex-centric graph computation on the Intel Optane DC persistent memory moduleen_US
dc.typeThesisen_US
dc.description.degreeM. Eng.en_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Scienceen_US
dc.identifier.oclc1227512186en_US
dc.description.collectionM.Eng. Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Scienceen_US
dspace.imported2021-01-06T19:33:50Zen_US
mit.thesis.degreeMasteren_US
mit.thesis.departmentEECSen_US


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