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Design and analysis of a memory hierarchy for a very high performance multiprocessor configuration

dc.contributor.advisorArvind.en_US
dc.contributor.authorTick, Evan Michaelen_US
dc.contributor.otherMassachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.en_US
dc.date.accessioned2005-08-04T19:11:27Z
dc.date.available2005-08-04T19:11:27Z
dc.date.copyright1982en_US
dc.date.issued1982en_US
dc.identifier.urihttp://hdl.handle.net/1721.1/15753
dc.descriptionThesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1982.en_US
dc.descriptionMICROFICHE COPY AVAILABLE IN ARCHIVES AND ENGINEERING.en_US
dc.descriptionVita.en_US
dc.descriptionBibliography: p. 204-221.en_US
dc.description.statementofresponsibilityby Evan Michael Tick.en_US
dc.format.extent212 p.en_US
dc.format.extent11927075 bytes
dc.format.extent11926835 bytes
dc.format.mimetypeapplication/pdf
dc.format.mimetypeapplication/pdf
dc.language.isoengen_US
dc.publisherMassachusetts Institute of Technologyen_US
dc.rightsM.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.en_US
dc.rights.urihttp://dspace.mit.edu/handle/1721.1/7582
dc.subjectElectrical Engineering and Computer Science.en_US
dc.subject.lcshMultiprocessorsen_US
dc.subject.lcshComputer storage devicesen_US
dc.subject.lcshComputer architectureen_US
dc.titleDesign and analysis of a memory hierarchy for a very high performance multiprocessor configurationen_US
dc.typeThesisen_US
dc.description.degreeM.S.en_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
dc.identifier.oclc09391247en_US


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