Wire delay models for global placement of ASICs
Author(s)Paskalev, Krassimir (Krassimir Ivanov), 1978-
Wire delay models for global placement of Application-Specific Integrated Circuits
Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
Michael Fu and Jacob K. White.
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A new model for the propagation delay between two logic gates for timing-driven global placement is proposed. The model is a function of the number of pins on the net, the half perimeter of the bounding box enclosing the net, and the half perimeter of the bounding box enclosing the driving pin and the sink pin. On a training set of two designs and testing set of another two, the proposed model is 31% more accurate than the current state-of-the-art model and has comparable computational complexity.
Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2002.Includes bibliographical references (leaves 28-29).This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
DepartmentMassachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
Massachusetts Institute of Technology
Electrical Engineering and Computer Science.