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dc.contributor.advisorMichael Fu and Jacob K. White.en_US
dc.contributor.authorPaskalev, Krassimir (Krassimir Ivanov), 1978-en_US
dc.contributor.otherMassachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.en_US
dc.date.accessioned2005-05-19T15:02:20Z
dc.date.available2005-05-19T15:02:20Z
dc.date.copyright2002en_US
dc.date.issued2002en_US
dc.identifier.urihttp://hdl.handle.net/1721.1/16855
dc.descriptionThesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2002.en_US
dc.descriptionIncludes bibliographical references (leaves 28-29).en_US
dc.descriptionThis electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.en_US
dc.description.abstractA new model for the propagation delay between two logic gates for timing-driven global placement is proposed. The model is a function of the number of pins on the net, the half perimeter of the bounding box enclosing the net, and the half perimeter of the bounding box enclosing the driving pin and the sink pin. On a training set of two designs and testing set of another two, the proposed model is 31% more accurate than the current state-of-the-art model and has comparable computational complexity.en_US
dc.description.statementofresponsibilityby Krassimir Paskalev.en_US
dc.format.extent29 leavesen_US
dc.format.extent475019 bytes
dc.format.extent474775 bytes
dc.format.mimetypeapplication/pdf
dc.format.mimetypeapplication/pdf
dc.language.isoengen_US
dc.publisherMassachusetts Institute of Technologyen_US
dc.rightsM.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.en_US
dc.rights.urihttp://dspace.mit.edu/handle/1721.1/7582
dc.subjectElectrical Engineering and Computer Science.en_US
dc.titleWire delay models for global placement of ASICsen_US
dc.title.alternativeWire delay models for global placement of Application-Specific Integrated Circuitsen_US
dc.typeThesisen_US
dc.description.degreeM.Eng.en_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
dc.identifier.oclc51588096en_US


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