A framework for analog circuit optimization
Author(s)
Mitros, Piotr, 1979-
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Other Contributors
Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
Advisor
L. Rafael Reif.
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This thesis presents a system for optimization of analog circuit topologies and component values. The topology is optimized using simulated annealing, while the component values are optimized using gradient descent. Local minima are avoided and constraints are kept through the use of coordinate transformations, as well as the use of default starting points for component values. The system is targeted for use in 3D integrated circuit design. The architecture is extendable, and is designed to eventually include capabilities for automated layout and mixed-signal design.
Description
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004. Includes bibliographical references (p. 49-50).
Date issued
2004Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer SciencePublisher
Massachusetts Institute of Technology
Keywords
Electrical Engineering and Computer Science.