| dc.contributor.advisor | L. Rafael Reif. | en_US |
| dc.contributor.author | Mitros, Piotr, 1979- | en_US |
| dc.contributor.other | Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. | en_US |
| dc.date.accessioned | 2005-09-26T20:31:15Z | |
| dc.date.available | 2005-09-26T20:31:15Z | |
| dc.date.copyright | 2004 | en_US |
| dc.date.issued | 2004 | en_US |
| dc.identifier.uri | http://hdl.handle.net/1721.1/28447 | |
| dc.description | Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004. | en_US |
| dc.description | Includes bibliographical references (p. 49-50). | en_US |
| dc.description.abstract | This thesis presents a system for optimization of analog circuit topologies and component values. The topology is optimized using simulated annealing, while the component values are optimized using gradient descent. Local minima are avoided and constraints are kept through the use of coordinate transformations, as well as the use of default starting points for component values. The system is targeted for use in 3D integrated circuit design. The architecture is extendable, and is designed to eventually include capabilities for automated layout and mixed-signal design. | en_US |
| dc.description.statementofresponsibility | by Piotr Mitros. | en_US |
| dc.format.extent | 50 p. | en_US |
| dc.format.extent | 1751877 bytes | |
| dc.format.extent | 1755745 bytes | |
| dc.format.mimetype | application/pdf | |
| dc.format.mimetype | application/pdf | |
| dc.language.iso | en_US | |
| dc.publisher | Massachusetts Institute of Technology | en_US |
| dc.rights | M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. | en_US |
| dc.rights.uri | http://dspace.mit.edu/handle/1721.1/7582 | |
| dc.subject | Electrical Engineering and Computer Science. | en_US |
| dc.title | A framework for analog circuit optimization | en_US |
| dc.type | Thesis | en_US |
| dc.description.degree | M.Eng. | en_US |
| dc.contributor.department | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science | |
| dc.identifier.oclc | 57016868 | en_US |
