Designing a processor in Bluespec

Author(s)
Dave, Nirav Hemant, 1982-
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Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
Advisor
Arvind.
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Abstract
In this thesis, we designed a 2-way out-of-order processor in Bluespec implementing the MIPS I integer ISA. A number of scheduling optimizations were then used to bring the initial design up to the same level of cycle-level concurrency as found in standard RTL-level designs. From this, a general design methodology is proposed to effectively express, debug, and optimize large Bluespec designs.
Description
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.
 
Includes bibliographical references (p. 67).
 
Date issued
2005
URI
http://hdl.handle.net/1721.1/30174
Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Publisher
Massachusetts Institute of Technology
Keywords
Electrical Engineering and Computer Science.
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