Improved handling of the decoding operation in the Presto compiler

Abstract

This thesis presents a research project on decoder related optimizations in HDL de- signs. The goal of the research is to improve design synthesis quality-of-result, mainly in terms of area; this involves sharing decoders driven by related inputs, and map decoders using fewer number of boolean gates. Algorithms presented in this thesis were implemented in the Presto HDL compiler. A series of tests were conducted using real-world HDL designs in order to determine how effective these optimizations are.