A comparator-based switched-capacitor pipelined analog-to-digital converter

Abstract

A new comparator-based switched-capacitor(CBSC) technique is proposed that eliminates the need for high gain op-amps in switched-capacitor circuits. The CBSC technique replaces the op-amp in switched-capacitor circuits with a comparator and a current source. Compared to op-amps, comparators suffer less from the negative effects of scaled CMOS. The technique is applicable to a broad class of sampled-data circuits including analog-to-digital converters, digital-to-analog converters, sample-and-holds, integrators and filters. As a proof of concept the technique is demonstrated in the design of a pipelined analog-to-digital converter. The prototype CBSC 1.5 b/stage pipelined ADC implemented in a 0.18 [mu]m CMOS process operates at 7.9MHz, achieves 8.6 effective bits of accuracy, and consumes 2.5mW of power. Sources of offset and nonlinearity are identified and analyzed. The analysis reveals the potential of the CBSC technique for lower power dissipation and provides design guidelines for energy efficient comparator-based switched-capacitor circuit design.