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Graph-based representations and coupled verification of VLSI schematics and layouts

dc.contributorBamji, Cyrus S.en_US
dc.date.accessioned2004-03-02T18:30:24Z
dc.date.available2004-03-02T18:30:24Z
dc.date.issued1989en_US
dc.identifier.otherno. 547en_US
dc.identifier.urihttp://hdl.handle.net/1721.1/4205
dc.descriptionIncludes bibliographical references (p. 199-202).en_US
dc.description.sponsorshipWork supported by the Air Force Office of Scientific Research. AFSOR 86-0164 Work supported by IBM and Analog Devices.en_US
dc.description.statementofresponsibilityCyrus S. Bamji.en_US
dc.format.extent202 p.en_US
dc.format.extent12241617 bytes
dc.format.mimetypeapplication/pdf
dc.language.isoengen_US
dc.publisherResearch Laboratory of Electronics, Massachusetts Institute of Technologyen_US
dc.relation.ispartofseriesTechnical report (Massachusetts Institute of Technology. Research Laboratory of Electronics) ; 547.en_US
dc.subject.lccTK7855.M41 R43 no.547en_US
dc.titleGraph-based representations and coupled verification of VLSI schematics and layoutsen_US


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