Strained SiGe-channel p-MOSFETs : impact of heterostructure design and process technology

Abstract

Conventional Si CMOS intrinsic device performance has improved by 17% per year over the last 30 years through scaling of the gate length of the MOSFET along with process innovations such as the super-steep retrograde channel doping and ultra shallow source-drain junctions. In order to continue performance scaling with gate length for the 90 nm node and beyond (physical gate length 45 nm) an increase in the carrier mobility through the introduction of strain to the Si channel was required. To continue this scaling down to gate lengths of 10 nm new channel materials with superior mobility will be required. Superior hole mobility (up to 10X enhancement over bulk Si channels) and compatibility with mainstream Si processing technology make compressively strained SiGe an attractive channel material for sub 45 nm p-MOSFETs. This research investigates strained SiGe as a suitable channel material for p-MOSFETs using SiGe grown pseudomorphically on both relaxed SiGe and bulk Si substrates. Some of the fundamental and technological challenges that must be faced in order to incorporate SiGe channel materials are addressed, including the impact of heterostructure composition and SiGe channel thickness on mobility and MOSFET off-state leakage, as well as critical thickness and thermal budget constraints. In particular, the impact of the strained channel thickness on mobility is analyzed in detail. This work provides a detailed analysis of the design space for the SiGe heterostructure required to evaluate the trade off's between mobility enhancement, subthreshold characteristics and ease of integration with conventional CMOS processing in order to determine the optimum device structure.