dc.contributor.advisor | Krste Asanović. | en_US |
dc.contributor.author | Khan, Asif I. (Asif Imtiaz) | en_US |
dc.contributor.other | Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. | en_US |
dc.date.accessioned | 2008-11-07T18:54:24Z | |
dc.date.available | 2008-11-07T18:54:24Z | |
dc.date.copyright | 2008 | en_US |
dc.date.issued | 2008 | en_US |
dc.identifier.uri | http://hdl.handle.net/1721.1/43033 | |
dc.description | Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008. | en_US |
dc.description | Includes bibliographical references (p. 49-50). | en_US |
dc.description.abstract | With the computer hardware industry and the academic world focused on multiprocessor systems, the RAMP project is aiming to provide the infrastructure for supporting high-speed emulation of large scale, massively-parallel multiprocessor systems using FPGAs. The RAMP design framework provides the platform for building this infrastructure. This research utilizes this design framework to emulate various microprocessor memory systems through a model built in an FPGA. We model both the latency and the bandwidth of memory systems through a parameterized emulation platform, thereby, demonstrating the validity of the design framework. We also show the efficiency of the framework through an evaluation of the utilized FPGA resources. | en_US |
dc.description.statementofresponsibility | by Asif I. Khan. | en_US |
dc.format.extent | 50 leaves | en_US |
dc.language.iso | eng | en_US |
dc.publisher | Massachusetts Institute of Technology | en_US |
dc.rights | M.I.T. theses are protected by
copyright. They may be viewed from this source for any purpose, but
reproduction or distribution in any format is prohibited without written
permission. See provided URL for inquiries about permission. | en_US |
dc.rights.uri | http://dspace.mit.edu/handle/1721.1/7582 | en_US |
dc.subject | Electrical Engineering and Computer Science. | en_US |
dc.title | Emulation of microprocessor memory systems using the RAMP design framework | en_US |
dc.type | Thesis | en_US |
dc.description.degree | S.M. | en_US |
dc.contributor.department | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science | |
dc.identifier.oclc | 243608011 | en_US |