Control of wafer-scale non-uniformity in chemical-mechanical planarization by face-up polishing
Author(s)Mau, Catherine (Catherine K.)
Massachusetts Institute of Technology. Dept. of Mechanical Engineering.
Jung-Hoon Chun and Nannaji Saka.
MetadataShow full item record
Chemical-mechanical planarization (CMP) is a key process in the manufacture of ultra-large-scale-integrated (ULSI) semiconductor devices. A major concern in CMP is non-uniform planarization, or polishing, at the wafer-scale - primarily as interconnect metal dishing and dielectric erosion. In conventional face-down CMP, the pad is much larger than the wafer and the wafer is always in contact with the pad. Thus, non-uniform polishing rate at the wafer-scale is due to variations in relative velocity, normal pressure, and especially slurry distribution at the wafer/pad interface. Wafer-scale polishing uniformity requirements are expected to be even more stringent in the future as the ULSI technology advances toward larger wafers (450 mm) and ever shrinking feature sizes (< 20 nm). This thesis presents the theory and experimental validation of a novel, face-up CMP architecture proposed for achieving a high degree, better than 95 percent of polishing uniformity at the wafer-scale. The novel design utilizes a small, perforated pad that contacts only a portion of the wafer during CMP. Polishing uniformity is achieved by progressively translating the pad away from the polished to the unpolished regions of the wafer. The theory is based on Preston's Law for material removal rate and an optimal algorithm for pad translation. CMP experiments were conducted on both blanket and patterned wafers to validate the theory. Polishing of blanket wafers by non-translating pads showed that the Preston constant is higher at the center of the pad due to increased slurry flow. Thus, perforations at the pad center were blocked to minimize the variation in Preston constant. Face-up polishing of patterned wafers with the blocked pad showed improved wafer-scale uniformity in material removal rate.(cont.) Dielectric erosion was below 30 nm, less than 5 percent of the interconnect depth, across a 100-mm circular polished region. However, dishing of the wider interconnects was much greater. Nevertheless, the variation in dishing across the 100 [mu]m region was less than 35 nm for linewidths ranging from 2.5 [mu]m to 100 [mu]m , also less than 5 percent. Based on the theory and experimental results, several suggestions for further improving face-up CMP to minimize Cu dishing and dielectric erosion are offered.
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Mechanical Engineering, 2008.Includes bibliographical references (leaves 132-135).
DepartmentMassachusetts Institute of Technology. Department of Mechanical Engineering
Massachusetts Institute of Technology