A data servicing subsystem for the Chidi reconfigurable processor

Abstract

Application Specific Integrated Circuits (ASICs) are often used to enhance system performance, especially when a General Purpose Processor (GPP) is too inefficient or ill suited to perform a specialized task. However, the time and hardware costs inherent in the development and implementation of such a solution can be quite expensive. The use of Field Programmable Gate Arrays (FPGAs) to implement a Reconfigurable Processor (RP) can help alleviate some of the overhead encountered with ASIC development. The RP is a dynamic processing node that can be configured in-circuit to compute any realizable function at run-time. After the function has finished execution, the RP can be reconfigured to compute a different function. This concept is illustrated with the reconfigurable, multimedia Chidi Processing System. A network of Chidi boards, each with a closely coupled GPP and RP, is used to execute a sequence of multimedia related functions. One of the main issues in utilizing a RP efficiently is the ability to provide it with data effectively. The design and implementation of a data servicing subsystem for the Chidi Reconfigurable Processor, in an effort to increase system performance, is the main focus of study. This research is supported by the Digital Life Consortium at the MIT Media Laboratory.