| dc.contributor | Baltus, Donald George. | en_US |
| dc.date.accessioned | 2004-03-03T22:15:29Z | |
| dc.date.available | 2004-03-03T22:15:29Z | |
| dc.date.issued | 1988 | en_US |
| dc.identifier.other | no. 535 | en_US |
| dc.identifier.uri | http://hdl.handle.net/1721.1/4957 | |
| dc.description | Also issued as Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1988. | en_US |
| dc.description | Includes bibliographical references. | en_US |
| dc.description.sponsorship | Supported by the U.S. Air Force--Office of Scientific Research. AFOSR-86-0164 Supported in part by a National Science Foundation Graduate Fellowship. Supported in part by Thinking Machines Corporation. 2305/B4 | en_US |
| dc.description.statementofresponsibility | Donald George Baltus. | en_US |
| dc.format.extent | ix, 194 p. | en_US |
| dc.format.extent | 10316361 bytes | |
| dc.format.mimetype | application/pdf | |
| dc.language.iso | eng | en_US |
| dc.publisher | Research Laboratory of Electronics, Massachusetts Institute of Technology | en_US |
| dc.relation.ispartofseries | Technical report (Massachusetts Institute of Technology. Research Laboratory of Electronics) ; 535. | en_US |
| dc.subject.lcc | TK7855.M41 R43 no.535 | en_US |
| dc.title | Generating efficient layouts from optimized MOS circuit schematics | en_US |
