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dc.contributor.advisorDuane S. Boning.en_US
dc.contributor.authorJohnson, Joy Marieen_US
dc.contributor.otherMassachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.en_US
dc.date.accessioned2010-03-24T20:39:33Z
dc.date.available2010-03-24T20:39:33Z
dc.date.copyright2009en_US
dc.date.issued2009en_US
dc.identifier.urihttp://hdl.handle.net/1721.1/52807
dc.descriptionThesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.en_US
dc.descriptionThis electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.en_US
dc.descriptionCataloged from student submitted PDF version of thesis.en_US
dc.descriptionIncludes bibliographical references (p. 95-99).en_US
dc.description.abstractProgression of technology nodes in integrated circuit design is only possible if there are sustainable, cost-efficient processes by which these designs can be implemented. As future technologies are increasing device density, shrinking device dimensions, and employing novel structures, semiconductor processing must also advance to effectively and eciently process these devices. Arguably one of the most critical, inefficient, poorly understood and costly processes is planarization. Thus, this thesis focuses on two types of planarization processes. Models of efficient and environmentally benign electrochemical-mechanical copper planarization (eCMP) are developed, with a focus on electrochemical mechanisms and wafer-scale uniformity. Specifically, previous models for eCMP are enhanced to consider the full electrochemical system driving planarization in eCMP. We explore the notion of electrochemical reactions at both the cathode and anode, in addition to lateral current flow in a time-averaged calculation. More ecient and accurate models for planarization of shallow-trench isolation (STI) structures are proposed, with a focus on die-scale and feature-scale uniformity. This thesis captures the fundamental weakness of CMP, pattern dependencies, and uses deposition prole effects as well as the pattern-density to more accurately model and physically represent STI structures during CMP. We model, for the first time, the evolution of pattern density as a function of time and step-height, and use layout biasing to account for deposition prole evolution for the accurate prediction of die and feature-scale CMP.en_US
dc.description.statementofresponsibilityby Joy Marie Johnson.en_US
dc.format.extent99 p.en_US
dc.language.isoengen_US
dc.publisherMassachusetts Institute of Technologyen_US
dc.rightsM.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.en_US
dc.rights.urihttp://dspace.mit.edu/handle/1721.1/7582en_US
dc.subjectElectrical Engineering and Computer Science.en_US
dc.titleModeling of advanced integrated circuit planarization processes : electrochemical-mechanical planarization (eCMP), STI CMP using non-conventional slurriesen_US
dc.title.alternativeModeling of advanced integrated circuit planarizationen_US
dc.title.alternativeElectrochemical-mechanical planarization (eCMP), STI CMP using non-conventional slurriesen_US
dc.typeThesisen_US
dc.description.degreeS.M.en_US
dc.contributor.departmentMassachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.en_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
dc.identifier.oclc550552475en_US


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