SSTA design methodology for low voltage operation

Abstract

Statistical process variations have long been an important design issue. But until recently, process variations have been global process variations, i.e., transistor parameters may vary from die to die but are constant within a die. With transistor geometries shrinking below 65nm, however, a new kind of statistical variation, known as Local or Intra-die variation, has become important for logic and memory. Local variations are primarily the result of variations in the number of dopant atoms in the channel of CMOS transistors. To achieve ultra-low power, ICs are being designed for VDD </- 0.5V. At these voltages, the stochastic delay resulting from local variations has standard deviation comparable to the nominal delay. In order to predict the statistical impact of local variations on circuit performance, it is necessary to develop the statistical models that accurately reflect local variations and to develop a computationally efficient algorithm for performing SSTA using these models. At low voltage (VDD </- 0.5V), circuit delay is a non-linear function of the transistor random variables. This greatly complicates the statistical analysis because the PDF of the circuit delay is non-Gaussian. Most of the current SSTA approaches that can handle non-Gaussian PDFs, have high computational complexities. In this work, a complete SSTA design methodology for local variations in logic timing at low voltage operation is presented. The approach can handle non-linear delays with non-Gaussian delay PDFs in a computationally efficient manner. The approach has been implemented using commercial CAD tools and integrated into commercially used IC design flow. Comparison with Monte-Carlo analysis demonstrates high accuracy of the approach.