A time-interleaved Zero-Crossing-Based analog-to-digital converter

Abstract

CMOS technology scaling has further reduced the output voltage swing and device gain, making it increasingly difficult to realize high-speed, high-gain op-amps with a stable feedback loop. The switched capacitor multiplier circuit in pipelined ADC is one application which has been hindered by op-amp limitations. Zero Crossing Based (ZCB) switched-capacitor topologies have been proposed as an alternative to op-amp based circuits because ZCB circuits do not suffer from the same CMOS scaling issues. This research applies ZCB techniques to Time Interleaved ADCs (TIADC). Mismatch between the individual ADCs, or channels, that make up the TIADC degrade its accuracy and is a fundamental design challenge. This research addresses the mismatch issue by investigating new circuit techniques to reduce offset error and timing skew. A new method to analyze noise in ZCB topologies is also presented. These methods were used to design a 2GS/S 8-bit time-interleaved, pipelined ZCB ADC. Although applied to ZCB ADCs, the timing skew correction topology and noise analysis method are applicable to other ADC topologies.