Fractionally spaced equalization for high-speed links
Author(s)Song, Sanquan, 1980-
FSE for high-speed links
Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
Vladimir M. Stojanović.
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As high-speed links enter the multi-Gb/s era, equalization and clock recovery designs become much more challenging. For conventional links, these two loops are separate with different performance metrics, resulting in sub-optimal performance. Fractionally spaced equalization (FSE) inherently unifies these two functions, and therefore is proposed for joint equalization and synchronization in this thesis. At the system level, this thesis introduces new adaptation techniques for both mesochronous and plesiochronous applications. For mesochronous systems, the divergence issue of the low-cost sign-sign least-mean-square (SSLMS) adaptive algorithm is solved by using update conditioning to effectively increase the quantization resolution. For plesiochronous systems, a digitally-controlled bit-skipping scheme is proposed for frequency offset compensation. At the circuit level, the voltage-time conversion technique is redesigned to build highspeed, linear and energy-efficient FSE filter taps, which are scalable to advanced technology nodes. All the information is processed by linear current integration, with all integrated currents independent of the channel voltages, avoiding the non-linear voltage-current transformation. Based on different voltage-to-time converter designs, two proof-of-concept FSE implementations have been fabricated in a 90-nm CMOS process. The first implementation is a 2-way interleaved 2-tap FSE, operating at 4.0 Gb/s, with 2.0 pJ/bit energy-efficiency and 4.3 bits of linearity, showing immunity to the sampling phase. Operating at higher rates (6.25 Gb/s), the second implementation is designed as a 4-way interleaved 2-tap FSE with a 1-tap DFE, which achieves 3.6 pJ/bit energy-efficiency and over 4.0 bits of linearity, demonstrating the convergence of the modified sign-sign least-mean-square (M-SSLMS) algorithm. A third implementation has been designed with on-chip coefficient adaptation loop and bit-skipping scheme for plesiochronous systems.
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.Cataloged from PDF version of thesis.Includes bibliographical references (p. 115-119).
DepartmentMassachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
Massachusetts Institute of Technology
Electrical Engineering and Computer Science.