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dc.contributor.advisorVladimir M. Stojanović.en_US
dc.contributor.authorSong, Sanquan, 1980-en_US
dc.contributor.otherMassachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.en_US
dc.date.accessioned2011-06-20T15:56:17Z
dc.date.available2011-06-20T15:56:17Z
dc.date.copyright2011en_US
dc.date.issued2011en_US
dc.identifier.urihttp://hdl.handle.net/1721.1/64588
dc.descriptionThesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.en_US
dc.descriptionCataloged from PDF version of thesis.en_US
dc.descriptionIncludes bibliographical references (p. 115-119).en_US
dc.description.abstractAs high-speed links enter the multi-Gb/s era, equalization and clock recovery designs become much more challenging. For conventional links, these two loops are separate with different performance metrics, resulting in sub-optimal performance. Fractionally spaced equalization (FSE) inherently unifies these two functions, and therefore is proposed for joint equalization and synchronization in this thesis. At the system level, this thesis introduces new adaptation techniques for both mesochronous and plesiochronous applications. For mesochronous systems, the divergence issue of the low-cost sign-sign least-mean-square (SSLMS) adaptive algorithm is solved by using update conditioning to effectively increase the quantization resolution. For plesiochronous systems, a digitally-controlled bit-skipping scheme is proposed for frequency offset compensation. At the circuit level, the voltage-time conversion technique is redesigned to build highspeed, linear and energy-efficient FSE filter taps, which are scalable to advanced technology nodes. All the information is processed by linear current integration, with all integrated currents independent of the channel voltages, avoiding the non-linear voltage-current transformation. Based on different voltage-to-time converter designs, two proof-of-concept FSE implementations have been fabricated in a 90-nm CMOS process. The first implementation is a 2-way interleaved 2-tap FSE, operating at 4.0 Gb/s, with 2.0 pJ/bit energy-efficiency and 4.3 bits of linearity, showing immunity to the sampling phase. Operating at higher rates (6.25 Gb/s), the second implementation is designed as a 4-way interleaved 2-tap FSE with a 1-tap DFE, which achieves 3.6 pJ/bit energy-efficiency and over 4.0 bits of linearity, demonstrating the convergence of the modified sign-sign least-mean-square (M-SSLMS) algorithm. A third implementation has been designed with on-chip coefficient adaptation loop and bit-skipping scheme for plesiochronous systems.en_US
dc.description.statementofresponsibilityby Sanquan Song.en_US
dc.format.extent119 p.en_US
dc.language.isoengen_US
dc.publisherMassachusetts Institute of Technologyen_US
dc.rightsM.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.en_US
dc.rights.urihttp://dspace.mit.edu/handle/1721.1/7582en_US
dc.subjectElectrical Engineering and Computer Science.en_US
dc.titleFractionally spaced equalization for high-speed linksen_US
dc.title.alternativeFSE for high-speed linksen_US
dc.typeThesisen_US
dc.description.degreePh.D.en_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
dc.identifier.oclc727061784en_US


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