MIT Libraries logoDSpace@MIT

MIT
View Item 
  • DSpace@MIT Home
  • MIT Libraries
  • MIT Theses
  • Graduate Theses
  • View Item
  • DSpace@MIT Home
  • MIT Libraries
  • MIT Theses
  • Graduate Theses
  • View Item
JavaScript is disabled for your browser. Some features of this site may not work without it.

Feature scaling of large, ballasted, field emission arrays

Author(s)
Guerrera, Stephen A. (Stephen Angelo)
Thumbnail
DownloadFull printable version (14.60Mb)
Other Contributors
Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
Advisor
Akintunde Ibitayo (Tayo) Akinwande.
Terms of use
M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582
Metadata
Show full item record
Abstract
Field emitters are an exciting technology for high-frequency, high-power applications because of their excellent free space electron transport, and their potential for high current density and high current, especially when they are used in an array format. However, a major challenge preventing the widespread use of this technology are the spatial and temporal variations that arise from non-uniformity in emitter tip radius and work function, respectively. To address the problems, various methods of controlling the supply of electrons to the emitter have been developed. One method of current limiting is the vertical ungated field effect transistor (FET), which uses the channel pinch-o and velocity saturation of carriers in silicon combined with a high aspect ratio to provide an effective method of controlling current. To reduce the operating voltage, and likewise the energy spread of the emitted electrons, we created vertical ungated FET current limiters that were 100 nm in diameter, 8 m tall, and had a pitch of 1 m that were patterned using optical lithography. These devices demonstrated excellent current saturation, with output conductances lower than 10??11 S. In addition, a fabrication process for building nano-sharp emitters on these high aspect ratio pillars was developed. Using this process tip radii of less than 6 nm were obtained on top of the pillars. Process and device simulations were performed that indicate it will be possible to integrate extraction gates with small apertures into this structure, allowing for stable, uniform emission at gate voltages under 20 V in future work.
Description
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.
 
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
 
Cataloged from student submitted PDF version of thesis.
 
Includes bibliographical references (p. 143-147).
 
Date issued
2011
URI
http://hdl.handle.net/1721.1/65970
Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Publisher
Massachusetts Institute of Technology
Keywords
Electrical Engineering and Computer Science.

Collections
  • Graduate Theses

Browse

All of DSpaceCommunities & CollectionsBy Issue DateAuthorsTitlesSubjectsThis CollectionBy Issue DateAuthorsTitlesSubjects

My Account

Login

Statistics

OA StatisticsStatistics by CountryStatistics by Department
MIT Libraries
PrivacyPermissionsAccessibilityContact us
MIT
Content created by the MIT Libraries, CC BY-NC unless otherwise noted. Notify us about copyright concerns.