Feature scaling of large, ballasted, field emission arrays

Abstract

Field emitters are an exciting technology for high-frequency, high-power applications because of their excellent free space electron transport, and their potential for high current density and high current, especially when they are used in an array format. However, a major challenge preventing the widespread use of this technology are the spatial and temporal variations that arise from non-uniformity in emitter tip radius and work function, respectively. To address the problems, various methods of controlling the supply of electrons to the emitter have been developed. One method of current limiting is the vertical ungated field effect transistor (FET), which uses the channel pinch-o and velocity saturation of carriers in silicon combined with a high aspect ratio to provide an effective method of controlling current. To reduce the operating voltage, and likewise the energy spread of the emitted electrons, we created vertical ungated FET current limiters that were 100 nm in diameter, 8 m tall, and had a pitch of 1 m that were patterned using optical lithography. These devices demonstrated excellent current saturation, with output conductances lower than 10??11 S. In addition, a fabrication process for building nano-sharp emitters on these high aspect ratio pillars was developed. Using this process tip radii of less than 6 nm were obtained on top of the pillars. Process and device simulations were performed that indicate it will be possible to integrate extraction gates with small apertures into this structure, allowing for stable, uniform emission at gate voltages under 20 V in future work.