Front-end circuits for a photonic analog-to-digital converter

Abstract

As the resolution of electrical ADCs gets limited at higher sampling rates due to sampling clock jitter, low-jitter mode-lock laser based photonic ADCs are starting to gain more attention. As well as low-jitter and high-linearity operation at very high speeds, photonic ADCs provide the opportunity to de-multiplex electrical signals to enable the parallel sampling of signals which increases the total sampling speed dramatically. However, even in photonic systems, a careful optimization between the degree of de-multiplexing, the optical non-linearities and receiver front-end noise has to be performed to enable resolution and sampling rate gains to materialize. Electrical components still constitute the bottleneck for a photonic ADC system. Photo-detector front-end, which is responsible for the current-voltage transformation of the samples, is one of the most critical components for the overall linearity, noise and jitter performance of photonic ADC systems. This work focuses on photo-detector front-ends and investigates the performance of several structures as well as evaluating the performance of photonic ADC systems depending on the amount of photo-detector current. Integrator and trans-impedance amplifier flavors of the front-end circuits are designed, implemented, simulated and laid out for 6 ENOB and 10 ENOB linearity and noise performance at 1GS/s. The circuits are implemented on 45 nm SOI process and integrated with on-chip photonic components which allow on-chip and off-chip ADC implementations.