Code compaction and parallelization for VLIW/DSP chip architectures

Author(s)
Petrov, Tsvetomir P. (Tsvetomir Petrov), 1974-
Thumbnail
DownloadFull printable version (3.223Mb)
Alternative title
Code compaction and parallelization for very long instruction word/discrete signal processing chip architectures
Advisor
Saman P. Amarasinghe.
Terms of use
M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582
Metadata
Show full item record
Description
Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1999.
 
Includes bibliographical references (p. 70-72).
 
Date issued
1999
URI
http://hdl.handle.net/1721.1/80111
Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Publisher
Massachusetts Institute of Technology
Keywords
Electrical Engineering and Computer Science
Collections