| dc.contributor.advisor | Saman P. Amarasinghe. | en_US |
| dc.contributor.author | Petrov, Tsvetomir P. (Tsvetomir Petrov), 1974- | en_US |
| dc.date.accessioned | 2013-08-22T18:52:11Z | |
| dc.date.available | 2013-08-22T18:52:11Z | |
| dc.date.copyright | 1999 | en_US |
| dc.date.issued | 1999 | en_US |
| dc.identifier.uri | http://hdl.handle.net/1721.1/80111 | |
| dc.description | Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1999. | en_US |
| dc.description | Includes bibliographical references (p. 70-72). | en_US |
| dc.description.statementofresponsibility | by Tsvetomir P. Petrov. | en_US |
| dc.format.extent | 72 p. | en_US |
| dc.language.iso | eng | en_US |
| dc.publisher | Massachusetts Institute of Technology | en_US |
| dc.rights | M.I.T. theses are protected by
copyright. They may be viewed from this source for any purpose, but
reproduction or distribution in any format is prohibited without written
permission. See provided URL for inquiries about permission. | en_US |
| dc.rights.uri | http://dspace.mit.edu/handle/1721.1/7582 | en_US |
| dc.subject | Electrical Engineering and Computer Science | en_US |
| dc.title | Code compaction and parallelization for VLIW/DSP chip architectures | en_US |
| dc.title.alternative | Code compaction and parallelization for very long instruction word/discrete signal processing chip architectures | en_US |
| dc.type | Thesis | en_US |
| dc.description.degree | M.Eng. | en_US |
| dc.contributor.department | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science | |
| dc.identifier.oclc | 43556637 | en_US |
