Chip-scale modeling of pattern dependencies in copper chemical mechanical polishing processes
Author(s)Gbondo-Tugbawa, Tamba Edward
Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
Duane S. Boning.
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Chemical mechanical polishing (CMP) has become a necessary processing step in the fabrication of copper interconnects. Copper CMP is recognized to suffer from pattern dependent problems such as dishing and erosion, which cause increased line resistance and non-uniformity within the die. The non-uniformity on one metal level can lead to cumulative non-uniformity on higher metal levels, leading to potential integration and manufacturing problems. Predictive pattern dependent models of copper CMP processes are therefore highly desirable for predicting dishing and erosion on random layouts, assessing the effectiveness of dummy fills in minimizing within-die non-uniformity, aiding in the generation of smart interconnect design rules, and identifying potential bulk copper clearing problems in multi-level metallization designs. In this thesis, the first predictive semi-physical chip-scale pattern dependent model for copper CMP processes is developed. A comprehensive model calibration methodology for any multi-step copper CMP process is also developed. The model takes into account the initial long range electroplated topography, the effective pattern density, and the initial local step heights within the arrays. The model also accounts for the temporal evolution of the bulk copper thickness during CMP, the temporal evolution of dishing and erosion, and the layout dependencies of dishing and erosion. A three step conventional copper CMP process experiment and a single step abrasive-free copper CMP process experiment are performed to test the accuracy of the model and the calibration methodology.(cont.) The results show that the model predicts the trends in the experimental data accurately, and fits the data to within acceptable errors. The model and the calibration methodology are integrated with an empirical pattern dependent electroplating model and calibration methodology, to form a chip-scale copper electroplating and CMP simulator. Once the models that form the simulator are calibrated for a given copper CMP process, and a given copper electroplating process, the simulator can be used to: (1) predict dishing and erosion across an entire chip, for a random layout; (2) assess the effectiveness of dummy fills in minimizing within-die non-uniformity; (3) identify bulk copper clearing problems in multi-level metallization designs; and (4) aid in the generation of smart interconnect design rules. Preliminary experimental results show that the simulator predicts dishing and erosion across an entire chip reasonably well, for a random layout.
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2002.Includes bibliographical references (p. 229-232).
DepartmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Massachusetts Institute of Technology
Electrical Engineering and Computer Science.