0.3V biopotential sensor interface for stress monitoring

Abstract

Miniaturized sensor nodes have a very tight power budget, especially in the case of implantables and health monitoring devices that require long operation lifetime. Exploiting low-voltage techniques in analog design can enable further power savings, which has not been explored much. However, for conventional analog-front-end (AFE) topologies, voltage scaling could potentially bring several limitations to the important performance metrics such as the linearity, robustness and the power-efficiency. This thesis work describes the design of a 0.3V biopotential sensor interface for stress monitoring applications, which achieves state-of-the-art power-efficiency, and ensures enough circuit reliability with reduced dynamic range requirement. The proposed sensor interface consists of an amplifier and an analog-to-digital converter (ADC). The simulated amplifier achieves 0.95nW power consumption with a power-efficiency-factor (PEF) of 1.57. With this power budget, the amplifier also presents large signal cancellation capability in order to reject the motion artifacts. The system, together with the ADC consumes 4.1nW power, and has an area of 0.2mm2 which makes the sensor interface suitable for wearable and implantable devices. The chip has been submitted for fabrication in a low power 65nm digital CMOS process, and the simulation results are presented.