A pipelined analog-to-digital converter with low-gain, low-bandwidth op-amps
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.
Anantha P. Chandrakasan and Hae-Seung Lee.
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Designing a high-gain, high-bandwidth op-amp for pipelined ADCs in fine-line CMOS technology has become increasingly challenging. In order to address this issue, this thesis presents the shadow-ADC-assisted digital calibration technique. The proposed technique relaxes op-amp performance requirements by removing op-amp-induced charge-transfer errors in the digital domain. A proof-of-concept pipelined ADC has been designed in 28nm FDSOI CMOS technology and is currently being fabricated.
Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2017.Cataloged from PDF version of thesis.Includes bibliographical references (pages 65-68).
DepartmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Massachusetts Institute of Technology
Electrical Engineering and Computer Science.