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dc.contributor.advisorAnantha P. Chandrakasan and Hae-Seung Lee.en_US
dc.contributor.authorJeong, Taehoonen_US
dc.contributor.otherMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.en_US
dc.date.accessioned2017-10-18T15:09:56Z
dc.date.available2017-10-18T15:09:56Z
dc.date.copyright2017en_US
dc.date.issued2017en_US
dc.identifier.urihttp://hdl.handle.net/1721.1/111917
dc.descriptionThesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2017.en_US
dc.descriptionCataloged from PDF version of thesis.en_US
dc.descriptionIncludes bibliographical references (pages 65-68).en_US
dc.description.abstractDesigning a high-gain, high-bandwidth op-amp for pipelined ADCs in fine-line CMOS technology has become increasingly challenging. In order to address this issue, this thesis presents the shadow-ADC-assisted digital calibration technique. The proposed technique relaxes op-amp performance requirements by removing op-amp-induced charge-transfer errors in the digital domain. A proof-of-concept pipelined ADC has been designed in 28nm FDSOI CMOS technology and is currently being fabricated.en_US
dc.description.statementofresponsibilityby Taehoon Jeong.en_US
dc.format.extent68 pagesen_US
dc.language.isoengen_US
dc.publisherMassachusetts Institute of Technologyen_US
dc.rightsMIT theses are protected by copyright. They may be viewed, downloaded, or printed from this source but further reproduction or distribution in any format is prohibited without written permission.en_US
dc.rights.urihttp://dspace.mit.edu/handle/1721.1/7582en_US
dc.subjectElectrical Engineering and Computer Science.en_US
dc.titleA pipelined analog-to-digital converter with low-gain, low-bandwidth op-ampsen_US
dc.typeThesisen_US
dc.description.degreeS.M.en_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
dc.identifier.oclc1005701141en_US


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