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dc.contributor.advisorTerry P. Orlando.en_US
dc.contributor.authorCord, Bryan M. (Bryan Michael), 1980-en_US
dc.contributor.otherMassachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.en_US
dc.date.accessioned2005-09-26T20:44:27Z
dc.date.available2005-09-26T20:44:27Z
dc.date.copyright2004en_US
dc.date.issued2004en_US
dc.identifier.urihttp://hdl.handle.net/1721.1/28491
dc.descriptionThesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.en_US
dc.descriptionIncludes bibliographical references (p. 113-116).en_US
dc.description.abstractA process was designed to fabricate Nb-AlOx-Nb Josephson junctions for quantum computing applications, with the goal of fabricating junctions as small as 0.2 [micro]m in diameter in a time span of roughly two weeks. The process was based on the doubly-planarized all-refractory technology for superconductive circuits (DPARTS) process currently used to fabricate these devices at MIT Lincoln Laboratory and streamlined by removing or replacing the most time-consuming steps and several optical layers. In addition, 248-nm (deep-UV) photolithography was employed for the first time in a Nb-based process, with the goal of improving resolution past that achievable by standard i-line lithography. The process has five optical layers, two wiring layers, and a via layer, and is intended to be used for rapid-turnaround evaluation of simple circuits requiring only two wiring layers. Anodization was used to produce a 50 nm film of NbOx to isolate the wiring layers, replacing the time-consuming oxide deposition and planarization used in the DPARTS process. A novel metallization and liftoff process employing surface-poisoning of chemically-amplified resist was used to deposit the contact layer. Several new plasma etching techniques were developed to selectively etch the various materials present in the process as well. The full process flow is briefly described in order of fabrication, followed by a detailed discussion of major process steps, issues, and results. Finally, testing results from devices fabricated using the new process are presented. An appendix detailing the design-of-experiment (DOE) approach used to characterize several process tools is also provided.en_US
dc.description.statementofresponsibilityby Bryan M. Cord.en_US
dc.format.extent116 p.en_US
dc.format.extent5353470 bytes
dc.format.extent5367441 bytes
dc.format.mimetypeapplication/pdf
dc.format.mimetypeapplication/pdf
dc.language.isoen_US
dc.publisherMassachusetts Institute of Technologyen_US
dc.rightsM.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.en_US
dc.rights.urihttp://dspace.mit.edu/handle/1721.1/7582
dc.subjectElectrical Engineering and Computer Science.en_US
dc.titleRapid fabrication of deep-submicron Josephson junctionsen_US
dc.typeThesisen_US
dc.description.degreeS.M.en_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
dc.identifier.oclc57303875en_US


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